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Semiconductor Electronics

JEE Main 2024 (Online) 9th April Evening ShiftMCQEasy📈 Topic in 53% papers+4−1
Ques. 1JEE Main 2024, 9 April (Evening Shift)

[figure] In the truth table of the above circuit the value of X and Y are :

  1. 1, 1
  2. 0, 1
  3. 1, 0
  4. 0, 0

Answer

(1) 1, 1

Solution

Upper AND gate gives A B; the lower AND gate receives A and B, so it gives A B.

The NOR gate then gives E = A B + A B (this is A B, the XOR output).

For A = 0, B = 1: A B = 0, A B = 0, so E = 0 = 1, hence X = 1.

For A = 1, B = 0: both products are again 0, so Y = 1.

Answer: (1)

Keep practising — Semiconductor Electronics

Ques. 2JEE Main 2024, 9 April (Evening Shift)

The I–V characteristics of an electronic device are shown in the figure. The device is : [figure]

  1. a solar cell
  2. a transistor which can be used as an amplifier
  3. a diode which can be used as a rectifier
  4. a zener diode which can be used as a voltage regulator
Ques. 3JEE Main 2024, 8 April (Morning Shift)

The output Y of following circuit for given inputs is : [figure]

  1. A B
  2. A B
  3. A B(A + B)
  4. 0
Ques. 4JEE Main 2024, 8 April (Evening Shift)

A potential divider circuit is connected with a dc source of 20 V, a light emitting diode of glow in voltage 1.8 V and a zener diode of breakdown voltage of 3.2 V. The length (PR) of the resistive wire is 20 cm. The minimum length of PQ to just glow the LED is cm. [figure]

Ques. 5JEE Main 2024, 6 April (Morning Shift)

The correct truth table for the following logic circuit is : [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
Ques. 6JEE Main 2024, 6 April (Evening Shift)

The acceptor level of a p-type semiconductor is 6 eV. The maximum wavelength of light which can create a hole would be : Given hc = 1242 eV nm.

  1. 407 nm
  2. 103.5 nm
  3. 414 nm
  4. 207 nm
Ques. 7JEE Main 2024, 5 April (Morning Shift)

Following gates section is connected in a complete suitable circuit. [figure] For which of the following combination, bulb will glow (ON) :

  1. A = 1, B = 1, C = 1, D = 0
  2. A = 1, B = 0, C = 0, D = 0
  3. A = 0, B = 0, C = 0, D = 1
  4. A = 0, B = 1, C = 1, D = 1
Ques. 8JEE Main 2024, 5 April (Evening Shift)

The output (Y) of logic circuit given below is 0 only when : [figure]

  1. A = 0, B = 0
  2. A = 0, B = 1
  3. A = 1, B = 0
  4. A = 1, B = 1
Ques. 9JEE Main 2024, 4 April (Morning Shift)

The value of net resistance of the network as shown in the given figure is : [figure]

  1. ( 3011 )
  2. 6
  3. ( 52 )
  4. ( 154 )
Ques. 10JEE Main 2024, 4 April (Evening Shift)

Which of the diode circuits shows correct biasing used for the measurement of dynamic resistance of p-n junction diode :

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
Ques. 11JEE Main 2024, 4 April (Evening Shift)

Identify the logic gate given in the circuit : [figure]

  1. OR gate
  2. NAND gate
  3. NOR gate
  4. AND gate

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