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Semiconductor Electronics · Question 15

JEE Main 2026 (Online) 24th January Evening ShiftMCQEasy📈 Topic in 58% papers+4−1
1

Identify the correct truth table of the given logic circuit. [figure]

  1. arrayccc A & B & Y \ 0 & 0 & 0 \ 0 & 1 & 0 \ 1 & 0 & 1 \ 1 & 1 & 0 array
  2. arrayccc A & B & Y \ 0 & 0 & 0 \ 0 & 1 & 1 \ 1 & 0 & 1 \ 1 & 1 & 0 array
  3. arrayccc A & B & Y \ 0 & 0 & 1 \ 0 & 1 & 1 \ 1 & 0 & 1 \ 1 & 1 & 0 array
  4. arrayccc A & B & Y \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 0 & 1 \ 1 & 1 & 0 array

Answer

(1) arrayccc A & B & Y \ 0 & 0 & 0 \ 0 & 1 & 0 \ 1 & 0 & 1 \ 1 & 1 & 0 array

Solution

Upper gate: AND gate with both inputs joined to A output = A A = A

Lower gate: NAND gate output = A B

Next gate: AND with inputs joined output = A B

Final AND gate:

Y = A A B = A ( A + B) = A B

Truth table: (0, 0) → 0, (0, 1) → 0, (1, 0) → 1, (1, 1) → 0

Answer: (1)

JEE Main 2026 (Online) 24th January Evening Shift

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2

The following diagram shows a Zener diode as a voltage regulator. The Zener diode is rated at Vz = 5 V and the desired current in load is 5 mA. The unregulated voltage source can supply up to 25 V. Considering the Zener diode can withstand four times the load current, the value of resistor Rs (shown in circuit) should be . [figure]

  1. 100
  2. 10
  3. 1000
  4. 4000
JEE Main 2026 (Online) 23rd January Morning Shift
3

For the given logic gate circuit, which of the following is the correct truth table? [figure]

  1. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 1 \ 1 & 1 & 0 \ 1 & 0 & 0 array
  2. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 1 & 1 \ 1 & 0 & 0 array
  3. arrayccc n & m & z \ 0 & 0 & 0 \ 0 & 1 & 1 \ 1 & 1 & 0 \ 1 & 0 & 1 array
  4. arrayccc n & m & z \ 0 & 0 & 1 \ 0 & 1 & 0 \ 1 & 1 & 0 \ 1 & 0 & 0 array
JEE Main 2026 (Online) 23rd January Evening Shift
4

Find the correct combination of A, B, C and D inputs which can cause the LED to glow. [figure]

  1. 1000
  2. 0011
  3. 0100
  4. 1101
JEE Main 2026 (Online) 22nd January Morning Shift
5

The correct truth table for the given input data of the following logic gate is : [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
JEE Main 2026 (Online) 22nd January Evening Shift
6

The given circuit works as : [figure]

  1. NOR gate
  2. OR gate
  3. AND gate
  4. NAND gate
JEE Main 2026 (Online) 21st January Morning Shift
7

The charge stored by the capacitor C in the given circuit in the steady state is . [figure]

  1. 7.5
  2. 5
  3. 10
  4. 12.5
JEE Main 2026 (Online) 21st January Evening Shift
8

The output voltage in the following circuit is (Consider ideal diode case) [figure]

  1. 0 V
  2. +5 V
  3. −5 V
  4. 10 V
JEE Main 2025 (Online) 8th April Evening Shift
9

In the following circuit, the reading of the ammeter will be (Take Zener breakdown voltage = 4 V) [figure]

  1. 60 mA
  2. 80 mA
  3. 10 mA
  4. 24 mA
JEE Main 2025 (Online) 7th April Morning Shift
10

Consider the following logic circuit. [figure] The output is Y = 0 when :

  1. A = 1 and B = 0
  2. A = 0 and B = 0
  3. A = 1 and B = 1
  4. A = 0 and B = 1
JEE Main 2025 (Online) 7th April Evening Shift
11

The Boolean expression Y = A BC + A C can be realised with which of the following gate configurations. Choose the correct answer from the options given below:

  1. B, C Only
  2. A, B, C Only
  3. A, B Only
  4. A, C Only
JEE Main 2025 (Online) 4th April Morning Shift

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