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Semiconductor Electronics

Previous year questions with solutions · 2000 – 2026

108Questions
36Papers covered
5.56% ↑25%Weightage in 2026
’00
’01
’02
’03
’04
’05
’06
’07
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’09
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’26
Year-wise statistics questions · papers · average per paper · weightage
YearQuestionsPapersAvg / paperWeightage
2026522.55.56% ↑25%
20252124.44% ↓25.9%
20246236.00% →0%
20233136.00% →0%
20226236.00% →0%
20213136.00% ↓10%
20203136.67% ↑50%
20192124.44% ↓33.3%
20183136.67% →0%
20173136.67% →0%
20166236.67% ↑50%
20154224.44% →0%
20142124.44% ↓33.3%
20136236.67% ↓23.8%
2012723.58.75% ↓1.2%
2011723.58.86% ↑2.5%
2010723.58.64% ↑41.2%
20093136.12% ↑43.9%
20082124.26% ↓33.3%
20073136.38% ↑6.4%
20063136.00% ↓43.6%
200551510.64% ↑22.3%
20044148.70% ↑13%
20034147.69% ↓9.6%
20024148.51% ↑39%
20013136.12% ↑37.8%
20002124.44%

⚠ 22 of these questions are out of the current syllabus (marked on the question).

30 questions · newest paper first

1

The output (Y) of the given logic implementation is similar to the output of an/a gate. [figure]

  1. OR
  2. NOR
  3. AND
  4. NAND
NEET (UG) 2025
2

A logic circuit provides the output Y as per the following truth table : [figure] The expression of the output Y is :

  1. A B + A
  2. A B + A
  3. B
  4. B
NEET (UG) 2024
3

The output (Y) of the given logic gate is similar to the output of an/a [figure]

  1. NAND gate
  2. NOR gate
  3. OR gate
  4. AND gate
NEET (UG) 2024
4

When the output of an OR gate is applied as input to a NOT gate, then the combination acts as a

  1. NAND gate
  2. NOR gate
  3. AND gate
  4. OR gate
RE-NEET (UG) 2024
5

The output Y for the inputs A and B of the given logic circuit is: [figure]

  1. A B
  2. A B
  3. A + B
  4. A + B
RE-NEET (UG) 2024
6

For the following logic circuit, the truth table is: [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
NEET (UG) 2023
7

[figure] The truth table for the given logic circuit is

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
NEET (UG) 2022
8

[figure] Identify the equivalent logic gate represented by the given circuit

  1. NAND
  2. OR
  3. NOR
  4. AND
NEET (UG) 2022 (Phase 2)
9

For the given circuit, the input digital signals are applied at the terminals A, B and C. What would be the output at the terminal y? [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
NEET (UG) 2021
10

For the logic circuit shown, the truth table is : [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
NEET (UG) 2020
11

The correct Boolean operation represented by the circuit diagram drawn is : [figure]

  1. OR
  2. NAND
  3. NOR
  4. AND
NEET (UG) 2019
12

In the combination of the following gates the output Y can be written in terms of inputs A and B as [figure]

  1. A.B
  2. A. B + A.B
  3. A. B + A.B
  4. A + B
NEET 2018
13

The given electrical network is equivalent to [figure]

  1. OR gate
  2. NOR gate
  3. NOT gate
  4. AND gate
NEET 2017
14

To get output 1 for the following circuit, the correct choice for the input is [figure]

  1. A = 1, B = 1, C = 0
  2. A = 1, B = 0, C = 1
  3. A = 0, B = 1, C = 0
  4. A = 1, B = 0, C = 0
NEET 2016 (Phase 1)
15

What is the output Y in the following circuit, when all the three inputs A, B, C are first 0 and then 1? [figure]

  1. 0, 1
  2. 0, 0
  3. 1, 0
  4. 1, 1
NEET 2016 (Phase 2)
16

Which logic gate is represented by the following combination of logic gates? [figure]

  1. AND
  2. NOR
  3. OR
  4. NAND
AIPMT 2015 (Cancelled)
17

The output (X) of the logic circuit shown in figure will be [figure]

  1. X = A . B
  2. X = A + B
  3. X = A . B
  4. X = A . B
NEET 2013
18

The output from a NAND gate is divided into two in parallel and fed to another NAND gate. The resulting gate is a [figure]

  1. AND gate
  2. NOR gate
  3. OR gate
  4. NOT gate
NEET 2013 (Karnataka)
19

To get an output Y = 1 in given circuit which of the following input will be correct ? [figure]

  1. A 1, B 0, C 0
  2. A 1, B 0, C 1
  3. A 1, B 1, C 0
  4. A 0, B 1, C 0
AIPMT 2012 (Mains)
20

The figure shows a logic circuit with two inputs A and B and the output C. The voltage wave forms across A, B and C are as given. The logic circuit gate is [figure]

  1. OR gate
  2. NOR gate
  3. AND gate
  4. NAND gate
AIPMT 2012 (Prelims)
21

Symbolic representations of four logic gates are shown as [figure] Pick out which ones are for AND, NAND and NOT gates, respectively

  1. (ii), (iii) and (iv)
  2. (iii), (ii) and (i)
  3. (iii), (ii) and (iv)
  4. (iii), (iv) and (ii)
AIPMT 2011 (Prelims)
22

The following figure shows a logic gate circuit with two inputs A and B and the output Y. The voltage waveforms of A, B and Y are as given. [figure] The logic gate is

  1. NOR gate
  2. OR gate
  3. AND gate
  4. NAND gate
AIPMT 2010 (Mains)
23

To get an output Y = 1 in given circuit which of the following input will be correct? [figure]

  1. A 1, B 0, C 0
  2. A 1, B 0, C 1
  3. A 1, B 1, C 0
  4. A 0, B 1, C 0
AIPMT 2010 (Prelims)
24

The device that can act as a complete electronic circuit is

  1. junction diode
  2. integrated circuit
  3. junction transistor
  4. zener diode
AIPMT 2010 (Prelims)
25

The symbolic representation of four logic gates are given below [figure] The logic symbols for OR, NOT and NAND gates are respectively

  1. (iv), (i), (iii)
  2. (iv), (ii), (i)
  3. (i), (iii), (iv)
  4. (iii), (iv), (ii)
AIPMT 2009
26

In the following circuit, the output Y for all possible inputs A and B is expressed by the truth table. [figure]

  1. [figure]
  2. [figure]
  3. [figure]
  4. [figure]
AIPMT 2007
27

The following figure shows a logic gate circuit with two inputs A and B and the output C. [figure] The voltage waveforms of A, B and C are as shown below. [figure] The logic circuit gate is

  1. OR gate
  2. AND gate
  3. NAND gate
  4. NOR gate
AIPMT 2006
28

The output of OR gate is 1

  1. if both inputs are zero
  2. if either or both inputs are 1
  3. only if both inputs are 1
  4. if either input is zero
AIPMT 2004
29

The given truth table is for which logic gate? [figure]

  1. NAND
  2. XOR
  3. NOR
  4. OR.
AIPMT 2002
30

The given truth table is for which logic gate [figure]

  1. NAND
  2. XOR
  3. NOR
  4. OR
AIPMT 2001